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| author | Anup Patel <anup.patel@wdc.com> | 2022-02-04 23:16:47 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-02-16 12:24:19 +1000 |
| commit | 2b6023987955a887aae3ad6882557960b2253a4f (patch) | |
| tree | dca20684b97bdb2a8ccb8be36d814ae62152d09b /scripts/modules/module_block.py | |
| parent | d028ac7512f1a781a5cba7659a1d25dc972afdd4 (diff) | |
| download | focaccia-qemu-2b6023987955a887aae3ad6882557960b2253a4f.tar.gz focaccia-qemu-2b6023987955a887aae3ad6882557960b2253a4f.zip | |
target/riscv: Implement AIA hvictl and hviprioX CSRs
The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-12-anup@brainfault.org [ Changes by AF: - Fix possible unintilised variable error in rmw_sie() ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/modules/module_block.py')
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