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| author | Anup Patel <anup.patel@wdc.com> | 2022-02-04 23:16:43 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-02-16 12:24:18 +1000 |
| commit | aa7508bbc63afe5c9fb65ce3353c9828ee12c4b3 (patch) | |
| tree | 946672d6dc3b1da942a683d37fc883c38f81e793 /scripts/modules/module_block.py | |
| parent | 32b0ada038629311aa90499a68de29473df7935d (diff) | |
| download | focaccia-qemu-aa7508bbc63afe5c9fb65ce3353c9828ee12c4b3.tar.gz focaccia-qemu-aa7508bbc63afe5c9fb65ce3353c9828ee12c4b3.zip | |
target/riscv: Add defines for AIA CSRs
The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-8-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/modules/module_block.py')
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