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| author | Alistair Francis <alistair23@gmail.com> | 2024-01-08 10:13:28 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-01-10 18:47:47 +1000 |
| commit | 71b76da33a1558bcd59100188f5753737ef6fa21 (patch) | |
| tree | 22701e05835602a7875548ed878c2ce9a675474a /scripts/mtest2make.py | |
| parent | 1525d8aa3a56610e1c72f5dd305ec86ebad41769 (diff) | |
| download | focaccia-qemu-71b76da33a1558bcd59100188f5753737ef6fa21.tar.gz focaccia-qemu-71b76da33a1558bcd59100188f5753737ef6fa21.zip | |
target/riscv: Ensure mideleg is set correctly on reset
Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor is enabled. We currently only set them on accesses to mideleg, but they aren't correctly set on reset. Let's ensure they are always the correct value. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1617 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240108001328.280222-4-alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/mtest2make.py')
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