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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-10-16 16:57:15 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-10-22 11:57:25 -0700 |
| commit | be46e0bf142d75c1978801d5d2c2394e7dfa304d (patch) | |
| tree | 150ac1f6f054013e113340b5ea095f770d00a557 /scripts/probe-gdb-support.py | |
| parent | a7cfd751fb269de4a93bf1658cb13911c7ac77cc (diff) | |
| download | focaccia-qemu-be46e0bf142d75c1978801d5d2c2394e7dfa304d.tar.gz focaccia-qemu-be46e0bf142d75c1978801d5d2c2394e7dfa304d.zip | |
disas/riscv: Fix vsetivli disassembly
The first immediate field is unsigned, whereas operand_vimm
extracts a signed value. There is no need to mask the result
with 'u'; just print the immediate with 'i'.
Fixes: 07f4964d178 ("disas/riscv.c: rvv: Add disas support for vector instructions")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'scripts/probe-gdb-support.py')
0 files changed, 0 insertions, 0 deletions