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| author | Fabian Aggeler <aggelerf@ethz.ch> | 2015-05-12 11:57:18 +0100 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-05-12 11:57:18 +0100 |
| commit | c5619bf9e8935aeb972c0bd935549e9ee0a739f2 (patch) | |
| tree | 5e8b6078292ecea8d4340a3f5ac188e8cf7e8593 /scripts/qapi-event.py | |
| parent | f9c6a7f1395c6d88a3bb1a0cb48811994709966e (diff) | |
| download | focaccia-qemu-c5619bf9e8935aeb972c0bd935549e9ee0a739f2.tar.gz focaccia-qemu-c5619bf9e8935aeb972c0bd935549e9ee0a739f2.zip | |
hw/intc/arm_gic: Change behavior of IAR writes
Grouping (GICv2) and Security Extensions change the behavior of IAR reads. Acknowledging Group0 interrupts is only allowed from Secure state and acknowledging Group1 interrupts from Secure state is only allowed if AckCtl bit is set. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-14-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-14-git-send-email-greg.bellows@linaro.org [PMM: simplify significantly by reusing the existing gic_get_current_pending_irq() rather than reimplementing the same logic here] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/qapi-event.py')
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