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| author | Jean-Christophe DUBOIS <jcd@tribudubois.net> | 2016-05-12 13:22:29 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-05-12 13:22:29 +0100 |
| commit | ec46eaa83a3c8c5677adc2ce0f956a7ab9948844 (patch) | |
| tree | 8ea9c1d28585710ec44b020016e94c8842cabf5c /scripts/qapi-event.py | |
| parent | c906a3a01582219b40a6b075ed28d4dd6f53d462 (diff) | |
| download | focaccia-qemu-ec46eaa83a3c8c5677adc2ce0f956a7ab9948844.tar.gz focaccia-qemu-ec46eaa83a3c8c5677adc2ce0f956a7ab9948844.zip | |
i.MX: Add i.MX6 SOC implementation.
For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 3 I2C controllers * 7 GPIO controllers * 6 SDHC controllers * 5 SPI controllers * 1 CCM device * 1 SRC device * various ROM/RAM areas. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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