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| author | Alex Bennée <alex.bennee@linaro.org> | 2014-03-17 16:31:47 +0000 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-03-17 16:31:47 +0000 |
| commit | 10113b6903c0256c1741918430b0304c5a60b7a8 (patch) | |
| tree | 83b6c459fa064cefa1ddb2c1d38fb354ae5d1ca0 /scripts/qapi-types.py | |
| parent | cf4ab1af296b8ef5d5a1dc65fda804b88ddd0553 (diff) | |
| download | focaccia-qemu-10113b6903c0256c1741918430b0304c5a60b7a8.tar.gz focaccia-qemu-10113b6903c0256c1741918430b0304c5a60b7a8.zip | |
target-arm: A64: Add last AdvSIMD Integer to FP ops
This adds the remaining [US]CVTF operations to the SIMD shift-immediate, scalar-shift-immediate, two-reg-misc and scalar-two-reg-misc groups of opcodes. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1394822294-14837-4-git-send-email-peter.maydell@linaro.org [PMM: added scalar 2-misc and scalar-shift-imm encodings] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/qapi-types.py')
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