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| author | Richard Henderson <rth@twiddle.net> | 2016-03-01 08:59:32 -0800 |
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| committer | Richard Henderson <rth@twiddle.net> | 2016-03-14 10:52:42 -0700 |
| commit | a657f79e32422634415c09f3f15c73d610297af5 (patch) | |
| tree | 4faccbb8e9f3433bb5dbd750fbfcb8c1e268280e /scripts/qapi-visit.py | |
| parent | 880f8486503b32a29b653a3c0b3cfc5432012f38 (diff) | |
| download | focaccia-qemu-a657f79e32422634415c09f3f15c73d610297af5.tar.gz focaccia-qemu-a657f79e32422634415c09f3f15c73d610297af5.zip | |
target-i386: Fix SMSW for 64-bit mode
In non-64-bit modes, the instruction always stores 16 bits. But in 64-bit mode, when the destination is a register, the instruction can write 32 or 64 bits. Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'scripts/qapi-visit.py')
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