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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-07-08 20:45:12 +0530 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-07-11 13:19:35 +0100 |
| commit | 0d935760346b7ea07cbf5f63667151198012c922 (patch) | |
| tree | b0997ab4334a9d8da88bc56f9e73f64911f0045c /scripts/qapi/commands.py | |
| parent | 285b1d5fcef3ef352333f08bde669551054fbee4 (diff) | |
| download | focaccia-qemu-0d935760346b7ea07cbf5f63667151198012c922.tar.gz focaccia-qemu-0d935760346b7ea07cbf5f63667151198012c922.zip | |
target/arm: Implement SME RDSVL, ADDSVL, ADDSPL
These SME instructions are nominally within the SVE decode space, so we add them to sve.decode and translate-sve.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/qapi/commands.py')
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