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| author | Víctor Colombo <victor.colombo@eldorado.org.br> | 2022-06-22 16:32:03 -0300 |
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| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-07-06 10:22:37 -0300 |
| commit | 59f11543e2ccd5cab283732a7c59aeeaa6790138 (patch) | |
| tree | 554317e1166dc54d0fc8d81e6d22143f617c97e4 /scripts/qapi/common.py | |
| parent | 21870aab36355ff5a1a0dbdb06d2071f3214cab2 (diff) | |
| download | focaccia-qemu-59f11543e2ccd5cab283732a7c59aeeaa6790138.tar.gz focaccia-qemu-59f11543e2ccd5cab283732a7c59aeeaa6790138.zip | |
target/ppc: Change FPSCR_* to follow POWER ISA numbering convention
FPSCR_* bit values in QEMU are in the 'inverted' order from what Power ISA defines (e.g. FPSCR.FI is bit 46 but is defined as 17 in cpu.h). Now that PPC_BIT_NR macro was introduced to fix this situation for the MSR bits, we can use it for the FPSCR bits too. Also, adjust the comments to make then fit in 80 columns Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220622193203.127698-1-victor.colombo@eldorado.org.br> [danielhb: fixed 'exceptio' typo in target/ppc/cpu.h] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'scripts/qapi/common.py')
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