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| author | Marc Zyngier <maz@kernel.org> | 2019-12-01 12:20:15 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-12-16 10:46:34 +0000 |
| commit | 93fbc983b29a2eb84e2f6065929caf14f99c3681 (patch) | |
| tree | d92702ce78c823872b4fd6cea0b0f1fc82749927 /scripts/qapi/common.py | |
| parent | 630fcd4d2ba37050329e0adafdc552d656ebe2f3 (diff) | |
| download | focaccia-qemu-93fbc983b29a2eb84e2f6065929caf14f99c3681.tar.gz focaccia-qemu-93fbc983b29a2eb84e2f6065929caf14f99c3681.zip | |
target/arm: Honor HCR_EL2.TID1 trapping requirements
HCR_EL2.TID1 mandates that access from EL1 to REVIDR_EL1, AIDR_EL1 (and their 32bit equivalents) as well as TCMTR, TLBTR are trapped to EL2. QEMU ignores it, making it harder for a hypervisor to virtualize the HW (though to be fair, no known hypervisor actually cares). Do the right thing by trapping to EL2 if HCR_EL2.TID1 is set. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191201122018.25808-3-maz@kernel.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/qapi/common.py')
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