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| author | Bin Meng <bmeng.cn@gmail.com> | 2019-09-06 09:20:10 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-09-17 08:42:48 -0700 |
| commit | af14c840418bee1b22e5b1bc403dcc8c69492517 (patch) | |
| tree | 432e45bec6780943fc6095493ba1d829a6bde658 /scripts/qapi/common.py | |
| parent | e1724d09a6dc090063cad9d88d9994b9f55f5716 (diff) | |
| download | focaccia-qemu-af14c840418bee1b22e5b1bc403dcc8c69492517.tar.gz focaccia-qemu-af14c840418bee1b22e5b1bc403dcc8c69492517.zip | |
riscv: sifive_u: Add PRCI block to the SoC
Add PRCI mmio base address and size mappings to sifive_u machine, and generate the corresponding device tree node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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