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| author | Aleksandar Rikalo <arikalo@wavecomp.com> | 2018-08-07 12:49:38 +0200 |
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| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-08-24 17:51:59 +0200 |
| commit | 9affc1c59279f482ff145e0371926f79b6448e3e (patch) | |
| tree | 7ce3d57869f58a9907cc0461e49685e9c583d23c /scripts/qapi/doc.py | |
| parent | 11d0fc10b7efe3d0404a71e855c0d9f521ce3d66 (diff) | |
| download | focaccia-qemu-9affc1c59279f482ff145e0371926f79b6448e3e.tar.gz focaccia-qemu-9affc1c59279f482ff145e0371926f79b6448e3e.zip | |
target/mips: Fix pre-nanoMIPS MT ASE instructions availability control
Use bits from configuration registers for availability control of MT ASE instructions, rather than only ISA_MT bit in insn_flags. This is done by adding a field in hflags for MT bit, and adding functions check_mt() and check_cp0_mt(). Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Diffstat (limited to 'scripts/qapi/doc.py')
0 files changed, 0 insertions, 0 deletions