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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-11-09 19:45:58 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-01-13 17:16:03 +0100 |
| commit | 64fdbae7e1bc6408204a3cf3b8e6a2e7d8e36fe2 (patch) | |
| tree | b0e863e58e9fe29dc6b1519e04c6d9804d97b04f /scripts/qapi/error.py | |
| parent | 785fd1a9afd5cb894f3e53753d732c7fbbb3d74a (diff) | |
| download | focaccia-qemu-64fdbae7e1bc6408204a3cf3b8e6a2e7d8e36fe2.tar.gz focaccia-qemu-64fdbae7e1bc6408204a3cf3b8e6a2e7d8e36fe2.zip | |
hw/net/xilinx_ethlite: Access TX_GIE register for each port
Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port TX_GIE. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_TX_GIE0] and s->regs[R_TX_GIE1] are now unused. Not a concern, this array will soon disappear. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-13-philmd@linaro.org>
Diffstat (limited to 'scripts/qapi/error.py')
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