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| author | Jiayi Li <lijiayi@eswincomputing.com> | 2024-07-01 10:25:53 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-07-18 12:08:44 +1000 |
| commit | 910c18a91738f9b77c5faf66e3534bb10d6e306e (patch) | |
| tree | 77a376419aaa47fb317ec435da3b6cbff83e8806 /scripts/qapi/error.py | |
| parent | ae4bdcef6fd3166264a47ed6a17cb9870e32306e (diff) | |
| download | focaccia-qemu-910c18a91738f9b77c5faf66e3534bb10d6e306e.tar.gz focaccia-qemu-910c18a91738f9b77c5faf66e3534bb10d6e306e.zip | |
target/riscv: Validate the mode in write_vstvec
Base on the riscv-privileged spec, vstvec substitutes for the usual stvec. Therefore, the encoding of the MODE should also be restricted to 0 and 1. Signed-off-by: Jiayi Li <lijiayi@eswincomputing.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20240701022553.1982-1-lijiayi@eswincomputing.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/qapi/error.py')
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