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authorLuc Michel <luc.michel@amd.com>2025-09-26 09:07:31 +0200
committerPeter Maydell <peter.maydell@linaro.org>2025-10-07 10:35:36 +0100
commit482f95526a52eff123b810953b6f5eb9674e279b (patch)
treec118a02b913816cdfe8501df61960754225845e1 /scripts/qapi/expr.py
parent1bec18fc13dce2f9a066fcb52b5d15b6d3141499 (diff)
downloadfocaccia-qemu-482f95526a52eff123b810953b6f5eb9674e279b.tar.gz
focaccia-qemu-482f95526a52eff123b810953b6f5eb9674e279b.zip
hw/arm/xlnx-versal: PMC IOU SCLR: refactor creation
Refactor the PMC IOU SLCR device creation using the VersalMap structure.
This is the first user of a shared IRQ using an OR gate. The OSPI
controller is reconnected to the SLCR.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250926070806.292065-14-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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