diff options
| author | Christophe Leroy <christophe.leroy@csgroup.eu> | 2022-01-28 13:15:01 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-01-28 13:15:01 +0100 |
| commit | 5aad0457eceec0085a289dde72e73f15db556b99 (patch) | |
| tree | fb7dd72af78c8eeb3a91502702bf850820d9f038 /scripts/qapi/expr.py | |
| parent | 6e3f09c28a2e1767dddaf08b2f1414cd57c6c909 (diff) | |
| download | focaccia-qemu-5aad0457eceec0085a289dde72e73f15db556b99.tar.gz focaccia-qemu-5aad0457eceec0085a289dde72e73f15db556b99.zip | |
target/ppc: 603: fix restore of GPRs 0-3 on rfi
After a TLB miss exception, GPRs 0-3 must be restored on rfi. This is managed by hreg_store_msr() which is called by do_rfi() However, hreg_store_msr() does it if MSR[TGPR] is unset in the passed MSR value. The problem is that do_rfi() is given the content of SRR1 as the value to be set in MSR, but TGPR bit is not part of SRR1 and that bit is used for something else and is sometimes set to 1, leading to hreg_store_msr() not restoring GPRs. So, do the same way as for POW bit, force clearing it. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Cedric Le Goater <clg@kaod.org> Cc: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220120103824.239573-1-christophe.leroy@csgroup.eu> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'scripts/qapi/expr.py')
0 files changed, 0 insertions, 0 deletions