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| author | Strahinja Jankovic <strahinjapjankovic@gmail.com> | 2022-12-26 23:02:58 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-01-12 16:50:19 +0000 |
| commit | edd3a59d5b98964ed72265346cb4dc7e9ffccd27 (patch) | |
| tree | bc4007ea9f6446f1cbbc1fee04774a7af2d1f9b7 /scripts/qapi/introspect.py | |
| parent | 423ec28bb8c20d9dfa68faef50699772899ab64d (diff) | |
| download | focaccia-qemu-edd3a59d5b98964ed72265346cb4dc7e9ffccd27.tar.gz focaccia-qemu-edd3a59d5b98964ed72265346cb4dc7e9ffccd27.zip | |
hw/misc: Allwinner A10 DRAM Controller Emulation
During SPL boot several DRAM Controller registers are used. Most important registers are those related to DRAM initialization and calibration, where SPL initiates process and waits until certain bit is set/cleared. This patch adds these registers, initializes reset values from user's guide and updates state of registers as SPL expects it. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20221226220303.14420-3-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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