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authorZhao Liu <zhao1.liu@intel.com>2025-07-11 18:21:33 +0800
committerPaolo Bonzini <pbonzini@redhat.com>2025-07-12 15:28:21 +0200
commit225aad5a7b78b3dc017996ab5b5e1b9249c036a0 (patch)
treea65a875a42a3fa179673be7c9145c42326414507 /scripts/qapi/main.py
parent216d9bb6d77162a93a0f09d72fdabfd252d941ce (diff)
downloadfocaccia-qemu-225aad5a7b78b3dc017996ab5b5e1b9249c036a0.tar.gz
focaccia-qemu-225aad5a7b78b3dc017996ab5b5e1b9249c036a0.zip
i386/cpu: Mark CPUID[0x80000005] as reserved for Intel
Per SDM, 0x80000005 leaf is reserved for Intel CPU, and its current
"assert" check blocks adding new cache model for non-AMD CPUs.

And please note, although Zhaoxin mostly follows Intel behavior,
this leaf is an exception [1].

So, with the compat property "x-vendor-cpuid-only-v2", for the machine
since v10.1, check the vendor and encode this leaf as all-0 only for
Intel CPU. In addition, drop lines_per_tag assertion in
encode_cache_cpuid80000005(), since Zhaoxin will use legacy Intel cache
model in this leaf - which doesn't have this field.

This fix also resolves 2 FIXMEs of legacy_l1d_cache_amd and
legacy_l1i_cache_amd:

/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */

In addition, per AMD's APM, update the comment of CPUID[0x80000005].

[1]: https://lore.kernel.org/qemu-devel/fa16f7a8-4917-4731-9d9f-7d4c10977168@zhaoxin.com/

Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250711102143.1622339-9-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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