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| author | Anup Patel <anup.patel@wdc.com> | 2022-02-04 23:16:46 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-02-16 12:24:19 +1000 |
| commit | d028ac7512f1a781a5cba7659a1d25dc972afdd4 (patch) | |
| tree | d48604427fc22e80246f43efbc8852e2fe2a7c39 /scripts/qapi/main.py | |
| parent | 43dc93af36dced9d23911be2ed6b0fe82bf3c42c (diff) | |
| download | focaccia-qemu-d028ac7512f1a781a5cba7659a1d25dc972afdd4.tar.gz focaccia-qemu-d028ac7512f1a781a5cba7659a1d25dc972afdd4.zip | |
target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
The AIA specification adds new CSRs for RV32 so that RISC-V hart can support 64 local interrupts on both RV32 and RV64. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-11-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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