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| author | Bernhard Beschow <shentey@gmail.com> | 2023-10-07 14:38:17 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2023-10-22 05:18:16 -0400 |
| commit | 64127940aeb674cb5d9d8d0ea4ca20591bf2b010 (patch) | |
| tree | fda087bb111d1e600fffc807cf94c76858ddaec4 /scripts/qapi/parser.py | |
| parent | 295385127e83a923e166f8b4fe1e543ee4540018 (diff) | |
| download | focaccia-qemu-64127940aeb674cb5d9d8d0ea4ca20591bf2b010.tar.gz focaccia-qemu-64127940aeb674cb5d9d8d0ea4ca20591bf2b010.zip | |
hw/isa/piix3: Wire PIC IRQs to ISA bus in host device
Thie PIIX3 south bridge implements both the PIC and the ISA bus, so wiring the interrupts there makes the device model more self-contained. Furthermore, this allows the ISA interrupts to be wired to internal child devices in pci_piix3_realize() which will be performed in subsequent patches. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20231007123843.127151-10-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'scripts/qapi/parser.py')
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