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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-08-13 17:11:48 +0100 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-08-25 10:48:48 +0100 |
| commit | fdcf2269c4e0e4f5ca3a389290a71d7aa98bd5c7 (patch) | |
| tree | f76078403ccb304148d3c0ac2884fbe34bf98617 /scripts/qapi/parser.py | |
| parent | 95351aa76c8f68564c4be547c1d19d9cabffc147 (diff) | |
| download | focaccia-qemu-fdcf2269c4e0e4f5ca3a389290a71d7aa98bd5c7.tar.gz focaccia-qemu-fdcf2269c4e0e4f5ca3a389290a71d7aa98bd5c7.zip | |
target/arm: Fix MVE 48-bit SQRSHRL for small right shifts
We got an edge case wrong in the 48-bit SQRSHRL implementation: if the shift is to the right, although it always makes the result smaller than the input value it might not be within the 48-bit range the result is supposed to be if the input had some bits in [63..48] set and the shift didn't bring all of those within the [47..0] range. Handle this similarly to the way we already do for this case in do_uqrshl48_d(): extend the calculated result from 48 bits, and return that if not saturating or if it doesn't change the result; otherwise fall through to return a saturated value. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'scripts/qapi/parser.py')
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