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| author | Chalapathi V <chalapathi.v@linux.ibm.com> | 2024-01-23 16:37:02 +1000 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-02-23 23:24:42 +1000 |
| commit | 5706b0064d6a78c32bf46f18910bc4e10dde2687 (patch) | |
| tree | 4a05fad717b2c03dcc41ef3289cee26e182e8d46 /scripts/qapi/schema.py | |
| parent | 1adf24708bf7f8506fab6f2d53530af0210e6658 (diff) | |
| download | focaccia-qemu-5706b0064d6a78c32bf46f18910bc4e10dde2687.tar.gz focaccia-qemu-5706b0064d6a78c32bf46f18910bc4e10dde2687.zip | |
hw/ppc: Add N1 chiplet model
The N1 chiplet handle the high speed i/o traffic over PCIe and others. The N1 chiplet consists of PowerBus Fabric controller, nest Memory Management Unit, chiplet control unit and more. This commit creates a N1 chiplet model and initialize and realize the pervasive chiplet model where chiplet control registers are implemented. This commit also implement the read/write method for the powerbus scom registers Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'scripts/qapi/schema.py')
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