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| author | Luc Michel <luc.michel@amd.com> | 2025-09-26 09:07:43 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-10-07 10:35:36 +0100 |
| commit | 0dfff625b5dafcb6cd722dd094ddc54c031e9169 (patch) | |
| tree | 7c78fe5384674adb6d0180847472254d6dee0637 /scripts/qapi/source.py | |
| parent | d95bf385567dc635f4cf275af118f3774e3b3d29 (diff) | |
| download | focaccia-qemu-0dfff625b5dafcb6cd722dd094ddc54c031e9169.tar.gz focaccia-qemu-0dfff625b5dafcb6cd722dd094ddc54c031e9169.zip | |
hw/arm/xlnx-versal: add support for GICv2
Add support for GICv2 instantiation in the Versal SoC. This is in preparation for the RPU refactoring. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-26-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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