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authorKlaus Jensen <k.jensen@samsung.com>2020-06-09 21:03:18 +0200
committerKevin Wolf <kwolf@redhat.com>2020-06-17 14:53:40 +0200
commitca247d35098d396db25233d5f554bd3098949d60 (patch)
tree8fde4b30593ed2cae39e539d962b0f78e7daac65 /scripts/qapi/source.py
parentb4529c5c3af69189b65b22906a35b09a7fe17960 (diff)
downloadfocaccia-qemu-ca247d35098d396db25233d5f554bd3098949d60.tar.gz
focaccia-qemu-ca247d35098d396db25233d5f554bd3098949d60.zip
hw/block/nvme: fix pin-based interrupt behavior
First, since the device only supports MSI-X or pin-based interrupt, if
MSI-X is not enabled, it should not accept interrupt vectors different
from 0 when creating completion queues.

Secondly, the irq_status NvmeCtrl member is meant to be compared to the
INTMS register, so it should only be 32 bits wide. And it is really only
useful when used with multi-message MSI.

Third, since we do not force a 1-to-1 correspondence between cqid and
interrupt vector, the irq_status register should not have bits set
according to cqid, but according to the associated interrupt vector.

Fix these issues, but keep irq_status available so we can easily support
multi-message MSI down the line.

Fixes: 5e9aa92eb1a5 ("hw/block: Fix pin-based interrupt behaviour of NVMe")
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Message-Id: <20200609190333.59390-8-its@irrelevant.dk>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
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