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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-02-08 12:58:02 +0000 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-13 14:14:54 +0000 |
| commit | f062d1447f2a80e7a5f593b8cb5ac7cab5e16eb0 (patch) | |
| tree | 7a3c8dc8bbee0e00dcde1b998d7a63b0329d1187 /scripts/qapi/source.py | |
| parent | 4f9584ed4bba8a57a3cb2fa48a682725005d530a (diff) | |
| download | focaccia-qemu-f062d1447f2a80e7a5f593b8cb5ac7cab5e16eb0.tar.gz focaccia-qemu-f062d1447f2a80e7a5f593b8cb5ac7cab5e16eb0.zip | |
target/arm: Mask CPSR_J when Jazelle is not enabled
The J bit signals Jazelle mode, and so of course is RES0 when the feature is not enabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200208125816.14954-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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