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| author | Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | 2020-02-24 15:09:22 +0530 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-28 16:14:57 +0000 |
| commit | 11411489da890ae40c182be7fa745c647e8ce399 (patch) | |
| tree | d5dfccb3bf091f06dede10850f31029440ab0104 /scripts/qapi/types.py | |
| parent | 5df2cfbc8b61e0c5d050a69814f713d2ba045ec5 (diff) | |
| download | focaccia-qemu-11411489da890ae40c182be7fa745c647e8ce399.tar.gz focaccia-qemu-11411489da890ae40c182be7fa745c647e8ce399.zip | |
arm_gic: Mask the un-supported priority bits
The GICv2 allows the implementation to implement a variable number of priority bits; unimplemented bits in the priority registers are read as zeros, writes ignored. We were previously always implementing a full 8 bits of priority, which is allowed but not what the real hardware typically does (which is usually to have 4 or 5 bits of priority). Add a new device property to allow the number of implemented property bits to be specified. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Message-id: 1582537164-764-2-git-send-email-sai.pavan.boddu@xilinx.com Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: improved commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/qapi/types.py')
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