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| author | Bin Meng <bmeng.cn@gmail.com> | 2019-09-06 09:19:55 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-09-17 08:42:45 -0700 |
| commit | 131f0932cf0194355cbcac326c93c2830ebd5148 (patch) | |
| tree | 2c70d3a3c06bce16441dd5c9cb9f04b8fa9dc3d4 /scripts/qapi/types.py | |
| parent | a2360c854fb56f9506d81be8b86ba577c0dbefc3 (diff) | |
| download | focaccia-qemu-131f0932cf0194355cbcac326c93c2830ebd5148.tar.gz focaccia-qemu-131f0932cf0194355cbcac326c93c2830ebd5148.zip | |
riscv: hw: Remove the unnecessary include of target/riscv/cpu.h
The inclusion of "target/riscv/cpu.h" is unnecessary in various sifive model drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/qapi/types.py')
0 files changed, 0 insertions, 0 deletions