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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-28 14:58:30 +0100 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-07-02 11:48:37 +0100 |
| commit | 2e6a4ce0f61d4be3d85a5a9e75d1fb39faa23664 (patch) | |
| tree | 2dd1dcfffacdb9b8d48b2374c6fe10dd69d83772 /scripts/qapi/types.py | |
| parent | d6f9e011e8643fb00303e3fec24dd1e424f3f5b3 (diff) | |
| download | focaccia-qemu-2e6a4ce0f61d4be3d85a5a9e75d1fb39faa23664.tar.gz focaccia-qemu-2e6a4ce0f61d4be3d85a5a9e75d1fb39faa23664.zip | |
target/arm: Implement MVE VSHLC
Implement the MVE VSHLC insn, which performs a shift left of the entire vector with carry in bits provided from a general purpose register and carry out bits written back to that register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
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