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authorBin Meng <bmeng.cn@gmail.com>2019-09-06 09:19:58 -0700
committerPalmer Dabbelt <palmer@sifive.com>2019-09-17 08:42:46 -0700
commit56449d20e937e807e4fc35fa3e5a38f7636e7046 (patch)
tree43aba52df5fbc31c9135873e04506163ddb773e8 /scripts/qapi/types.py
parent9baa9f7c9f651dfc7ee8a4abd46c4036f6841f64 (diff)
downloadfocaccia-qemu-56449d20e937e807e4fc35fa3e5a38f7636e7046.tar.gz
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riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.

Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/qapi/types.py')
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