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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-02-14 11:46:40 -0800 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-21 16:07:00 +0000 |
| commit | 78cedfabd53b6f64e7e64fc84878d848e5df1d08 (patch) | |
| tree | 71dc8e562872b79199cdf2f032664a0c2db93f0a /scripts/qapi/types.py | |
| parent | 9e946eaba87916c43aaf0b2760bd5d5a54187c7b (diff) | |
| download | focaccia-qemu-78cedfabd53b6f64e7e64fc84878d848e5df1d08.tar.gz focaccia-qemu-78cedfabd53b6f64e7e64fc84878d848e5df1d08.zip | |
target/arm: Flush high bits of sve register after AdvSIMD EXT
Writes to AdvSIMD registers flush the bits above 128. Buglink: https://bugs.launchpad.net/bugs/1863247 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200214194643.23317-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/qapi/types.py')
0 files changed, 0 insertions, 0 deletions