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| author | Yi Chen <chenyi2000@zju.edu.cn> | 2023-04-06 18:15:59 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | d6db7c975e2e0d60850043ea8f208dd446a61d0a (patch) | |
| tree | 6ffce401b6785a47d3836dd9aad0691f0e98509f /scripts/qapi/types.py | |
| parent | 9ba63f9442067729c3fe41c88b1eb414874d46ea (diff) | |
| download | focaccia-qemu-d6db7c975e2e0d60850043ea8f208dd446a61d0a.tar.gz focaccia-qemu-d6db7c975e2e0d60850043ea8f208dd446a61d0a.zip | |
target/riscv: fix H extension TVM trap
- Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled. - Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled. - Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA. - Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes SFENCE.VMA/SINVAL.VMA or VS-mode executes SFENCE.VMA/SINVAL.VMA with HSTATUS.VTVM enabled. - Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes HFENCE.GVMA/HFENCE.VVMA/HINVAL.GVMA/HINVAL.VVMA. Signed-off-by: Yi Chen <chenyi2000@zju.edu.cn> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406101559.39632-1-chenyi2000@zju.edu.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/qapi/types.py')
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