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| author | Andrew Baumann <Andrew.Baumann@microsoft.com> | 2017-03-14 11:28:54 +0000 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-03-14 11:28:54 +0000 |
| commit | 6ecd0b6ba0591ef280ed984103924d4bdca5ac32 (patch) | |
| tree | ea13414813639fb2c050d0188ad70375592443f8 /scripts/qapi2texi.py | |
| parent | 94b5d57d2f5a3c849cecd65e424bb6f50b998df9 (diff) | |
| download | focaccia-qemu-6ecd0b6ba0591ef280ed984103924d4bdca5ac32.tar.gz focaccia-qemu-6ecd0b6ba0591ef280ed984103924d4bdca5ac32.zip | |
target/arm: implement armv8 PMUSERENR (user-mode enable bits)
In armv8, this register implements more than a single bit, with fine-grained enables for read access to event counters, cycles counters, and write access to the software increment. This change implements those checks using custom access functions for the relevant registers. Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 20170228215801.10472-2-Andrew.Baumann@microsoft.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: move a couple of access functions to be only compiled ifndef CONFIG_USER_ONLY to avoid compiler warnings] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/qapi2texi.py')
0 files changed, 0 insertions, 0 deletions