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authorMichael Clark <mjc@sifive.com>2018-12-14 00:18:39 +0000
committerPalmer Dabbelt <palmer@sifive.com>2018-12-20 12:08:43 -0800
commitef9e41df680a494dec92fe8d166cb2bc531b29a4 (patch)
treeeead798d0216809c942f854006fc22f1d10dd72b /scripts/qapi
parent9543fdaf223aac0313638752abfb3d6c2cf2169c (diff)
downloadfocaccia-qemu-ef9e41df680a494dec92fe8d166cb2bc531b29a4.tar.gz
focaccia-qemu-ef9e41df680a494dec92fe8d166cb2bc531b29a4.zip
RISC-V: Fix CLINT timecmp low 32-bit writes
A missing shift made updates to the low order bits
of timecmp erroneously copy the old low order bits
into the high order bits of the 64-bit timecmp
register. Add the missing shift and rename timecmp
local variables to timecmp_hi and timecmp_lo.

This bug didn't show up as the low order bits are
usually written first followed by the high order
bits meaning the high order bits contained an invalid
value between the timecmp_lo and timecmp_hi update.

Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Co-Authored-by: Johannes Haring <johannes.haring@gmx.net>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/qapi')
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