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| author | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-23 17:26:58 +0200 |
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| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-29 14:13:47 +0100 |
| commit | eab0bdb07cbed1131be2d1f541059c7b96b05e32 (patch) | |
| tree | ac7bdd7611cf5a0d253491b4220a733e4482d351 /scripts/qemu.py | |
| parent | a031ac61619294ae473a78d1834e757fad8b59e5 (diff) | |
| download | focaccia-qemu-eab0bdb07cbed1131be2d1f541059c7b96b05e32.tar.gz focaccia-qemu-eab0bdb07cbed1131be2d1f541059c7b96b05e32.zip | |
target/mips: Amend MXU instruction opcodes
Amend MXU instruction opcodes. Pool04 is actually only instruction OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit subfield 'aptn1'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'scripts/qemu.py')
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