diff options
| author | Sven Schnelle <svens@stackframe.org> | 2019-01-29 20:14:02 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-02-06 10:49:21 +0000 |
| commit | 68aa851aa21741ab0a3c019b641d6ce72f68b3d5 (patch) | |
| tree | d9e8ac235202070473020f2fcb63d0a59a839145 /scripts/qemugdb/aio.py | |
| parent | 5c41496dd780fed67eadd64c59fc2cf21717ecf0 (diff) | |
| download | focaccia-qemu-68aa851aa21741ab0a3c019b641d6ce72f68b3d5.tar.gz focaccia-qemu-68aa851aa21741ab0a3c019b641d6ce72f68b3d5.zip | |
target/hppa: fix PSW Q bit behaviour to match hardware
PA-RISC specification says: "Setting the PSW Q-bit, PSW{28}, to 1
with this instruction, if it was not already 1, is an undefined
operation." However, at least HP-UX 10.20 sets the Q bit from 0 to 1
with the SSM instruction. Tested this both on HP9000/712 and
HP9000/785/C3750, both machines set the Q bit from 0 to 1 without
exception. This makes HP-UX 10.20 progress a little bit further.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Message-Id: <20190129191402.29539-1-svens@stackframe.org>
[rth: Add a comment to the code as well.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'scripts/qemugdb/aio.py')
0 files changed, 0 insertions, 0 deletions