diff options
| author | Michael Clark <mjc@sifive.com> | 2019-01-14 23:58:08 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-02-11 15:56:21 -0800 |
| commit | 7f2b5ff125d518a7fff9f6a4c633e3063fd75ec3 (patch) | |
| tree | b66e36ce977606f1045348ca8b3b4c0871a64e4d /scripts/qemugdb/coroutine.py | |
| parent | 533b8f8877d4e3e8bf2b57e633a84afe27c14429 (diff) | |
| download | focaccia-qemu-7f2b5ff125d518a7fff9f6a4c633e3063fd75ec3.tar.gz focaccia-qemu-7f2b5ff125d518a7fff9f6a4c633e3063fd75ec3.zip | |
RISC-V: Implement mstatus.TSR/TW/TVM
This adds the necessary minimum to support S-mode virtualization for priv ISA >= v1.10 Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Co-authored-by: Matthew Suozzo <msuozzo@google.com> Co-authored-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/qemugdb/coroutine.py')
0 files changed, 0 insertions, 0 deletions