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| author | Cédric Le Goater <clg@kaod.org> | 2019-03-07 23:35:36 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-03-12 14:33:04 +1100 |
| commit | 6f89f48e56723005b64260d2ab079a015db3ed64 (patch) | |
| tree | 153818bd655ace57cb0c7afe957b6ac2bc8285f3 /scripts/qemugdb/timers.py | |
| parent | c38536bc80fa0b8f44db50a3190bfd241143ab0b (diff) | |
| download | focaccia-qemu-6f89f48e56723005b64260d2ab079a015db3ed64.tar.gz focaccia-qemu-6f89f48e56723005b64260d2ab079a015db3ed64.zip | |
ppc/pnv: lpc: fix OPB address ranges
The PowerNV LPC Controller exposes different sets of registers for each of the functional units it encompasses, among which the OPB (On-Chip Peripheral Bus) Master and Arbitrer and the LPC HOST Controller. The mapping addresses of each register range are correct but the sizes are too large. Fix the sizes and define the OPB Arbitrer range to fill the gap between the OPB Master registers and the LPC HOST Controller registers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'scripts/qemugdb/timers.py')
0 files changed, 0 insertions, 0 deletions