summary refs log tree commit diff stats
path: root/scripts/qemugdb/timers.py
diff options
context:
space:
mode:
authorMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>2019-03-07 18:05:20 +0000
committerDavid Gibson <david@gibson.dropbear.id.au>2019-03-12 14:33:04 +1100
commitd59d1182b14fcdad350108012fb015e6c2d355f0 (patch)
treea53994758e0ee72308d682ae18fe4068566f708e /scripts/qemugdb/timers.py
parent8a14d31b00ae82ed430806bac96962b73fe6967f (diff)
downloadfocaccia-qemu-d59d1182b14fcdad350108012fb015e6c2d355f0.tar.gz
focaccia-qemu-d59d1182b14fcdad350108012fb015e6c2d355f0.zip
target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
Now that all VSX registers are stored in host endian order, there is no need
to go via different accessors depending upon the register number. Instead we
introduce vsr64_offset() and use it directly from within get_cpu_vsr{l,h}() and
set_cpu_vsr{l,h}().

This also allows us to rewrite avr64_offset() and fpr_offset() in terms of the
new vsr64_offset() function to more clearly express the relationship between the
VSX, FPR and VMX registers, and also remove vsrl_offset() which is no longer
required.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20190307180520.13868-8-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'scripts/qemugdb/timers.py')
0 files changed, 0 insertions, 0 deletions