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| author | Suraj Jitindar Singh <sjitindarsingh@gmail.com> | 2017-01-13 17:28:23 +1100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-02-02 09:30:07 +1100 |
| commit | 6925f12f4f02e55c73e738cb9e91e8cda2f23358 (patch) | |
| tree | 826860c546a274eb5a2efa352444a10b8f1cd5ff /scripts/qemugdb | |
| parent | 76134d48b3a526ec5f5dec15630c51559577b2bf (diff) | |
| download | focaccia-qemu-6925f12f4f02e55c73e738cb9e91e8cda2f23358.tar.gz focaccia-qemu-6925f12f4f02e55c73e738cb9e91e8cda2f23358.zip | |
target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation
We are calculating the authority mask register key value wrong. The pte entry contains the key value with the two upper bits and the three lower bits stored separately. We should use these two portions to get a 5 bit value, not or them together which will only give us a 3 bit value. Fix this. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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