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| author | Frank Chang <frank.chang@sifive.com> | 2021-12-28 20:57:17 +0800 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2022-01-04 08:50:28 +0100 |
| commit | b66f73a0cb312c81470433dfd5275d2824bb89de (patch) | |
| tree | 9511c1061bfbbed6cab3587bf67a25792944c5aa /scripts/simplebench/bench-example.py | |
| parent | 6947feca588670a0443d3e8892e6e20c6acb491c (diff) | |
| download | focaccia-qemu-b66f73a0cb312c81470433dfd5275d2824bb89de.tar.gz focaccia-qemu-b66f73a0cb312c81470433dfd5275d2824bb89de.zip | |
hw/sd: Add SDHC support for SD card SPI-mode
In SPI-mode, SD card's OCR register: Card Capacity Status (CCS) bit is not set to 1 correclty when the assigned SD image size is larger than 2GB (SDHC). This will cause the SD card to be indentified as SDSC incorrectly. CCS bit should be set to 1 if we are using SDHC. Also, as there's no power up emulation in SPI-mode. The OCR register: Card power up status bit bit (busy) should also be set to 1 when reset. (busy bit is set to LOW if the card has not finished the power up routine.) Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211228125719.14712-1-frank.chang@sifive.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'scripts/simplebench/bench-example.py')
0 files changed, 0 insertions, 0 deletions