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| author | Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> | 2020-02-23 15:28:06 +0500 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-03-16 17:03:51 -0700 |
| commit | c5969a3a3c2cb9ea02ffb7e86acb059d3cf8c264 (patch) | |
| tree | 081053039d7613158c1214c406369afe4a336c35 /scripts/simplebench/bench-example.py | |
| parent | c6fc0fc1a71a0cb09b472cf36dded3c52bd77880 (diff) | |
| download | focaccia-qemu-c5969a3a3c2cb9ea02ffb7e86acb059d3cf8c264.tar.gz focaccia-qemu-c5969a3a3c2cb9ea02ffb7e86acb059d3cf8c264.zip | |
target/riscv: Fix VS mode interrupts forwarding.
Currently riscv_cpu_local_irq_pending is used to find out pending interrupt and VS mode interrupts are being shifted to represent S mode interrupts in this function. So when the cause returned by this function is passed to riscv_cpu_do_interrupt to actually forward the interrupt, the VS mode forwarding check does not work as intended and interrupt is actually forwarded to hypervisor. This patch fixes this issue. Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'scripts/simplebench/bench-example.py')
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