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| author | Rabin Vincent <rabinv@axis.com> | 2016-08-15 13:59:32 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2016-09-28 11:30:59 +0200 |
| commit | ceffd34e8589a9a4f18849a21ae1fecaef3af02e (patch) | |
| tree | 6c66889ab531bb93e0d73a7add944c7dac640e0c /scripts/simpletrace.py | |
| parent | 17bc37b75ea4c33a6f36f073a67df687bef840c9 (diff) | |
| download | focaccia-qemu-ceffd34e8589a9a4f18849a21ae1fecaef3af02e.tar.gz focaccia-qemu-ceffd34e8589a9a4f18849a21ae1fecaef3af02e.zip | |
target-cris: add v17 CPU
In the CRIS v17 CPU an ADDC (add with carry) instruction has been added compared to the v10 instruction set. Assembler syntax: ADDC [Rs],Rd ADDC [Rs+],Rd Size: Dword Description: The source data is added together with the carry flag to the destination register. The size of the operation is dword. Operation: Rd += s + C-flag; Flags affected: S R P U I X N Z V C - - - - - 0 * * * * Instruction format: ADDC [Rs],Rd +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs) | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Instruction format: ADDC [Rs+],Rd +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs) | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ [EI: Shorten 80+ lines] Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Rabin Vincent <rabinv@axis.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'scripts/simpletrace.py')
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