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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-02-03 13:46:33 +0000 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-02-03 13:46:33 +0000 |
| commit | 6a43e0b6e1f6bcd6b11656967422f4217258200a (patch) | |
| tree | 810246be506405944d67dace0851d438a60ef29b /scripts/tracetool/backend/log.py | |
| parent | a43e68a08bd0d723cc7e480e422a1008a5bb78a9 (diff) | |
| download | focaccia-qemu-6a43e0b6e1f6bcd6b11656967422f4217258200a.tar.gz focaccia-qemu-6a43e0b6e1f6bcd6b11656967422f4217258200a.zip | |
target-arm: Make various system registers visible to EL3
The AArch64 system registers DACR32_EL2, IFSR32_EL2, SPSR_IRQ, SPSR_ABT, SPSR_UND and SPSR_FIQ are visible and fully functional from EL3 even if the CPU has no EL2 (unlike some others which are RES0 from EL3 in that configuration). Move them from el2_cp_reginfo[] to v8_cp_reginfo[] so they are always present. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1453227802-9991-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'scripts/tracetool/backend/log.py')
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