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| author | David Gibson <david@gibson.dropbear.id.au> | 2016-02-09 09:28:43 +1000 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-02-17 09:59:30 +1100 |
| commit | 808bc3b069fdb5fc660f89e6bc7774eeefdc97ea (patch) | |
| tree | f472575858ac71eb23b54d2639026fdb25724811 /scripts/tracetool/backend/log.py | |
| parent | b7f0bbd2590a22be4c707e27f85e2334158e83aa (diff) | |
| download | focaccia-qemu-808bc3b069fdb5fc660f89e6bc7774eeefdc97ea.tar.gz focaccia-qemu-808bc3b069fdb5fc660f89e6bc7774eeefdc97ea.zip | |
target-ppc: Include missing MMU models for SDR1 in info registers
The HMP command "info registers" produces somewhat different information on different ppc cpu variants. For those with a hash MMU it's supposed to include the SDR1, DAR and DSISR registers related to the MMU. However, the switch is missing a couple of MMU model variants, meaning we will miss out this information on certain CPUs which should have it. This patch corrects the oversight. (Really these MMU model IDs need a big cleanup, but we might as well fix the bug in the interim). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Diffstat (limited to 'scripts/tracetool/backend/log.py')
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