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| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2019-01-07 15:23:46 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-01-07 15:23:46 +0000 |
| commit | aee63b07fd1c2316d96dff0a6217288a630ce147 (patch) | |
| tree | a80da0cf54e497e45332dba46df7737767c3e884 /scripts/tracetool/backend/syslog.py | |
| parent | c38c37ac979c54b09293eb11061aa0e534e0f3bf (diff) | |
| download | focaccia-qemu-aee63b07fd1c2316d96dff0a6217288a630ce147.tar.gz focaccia-qemu-aee63b07fd1c2316d96dff0a6217288a630ce147.zip | |
hw/arm: versal: Plug memory leaks
Plug a couple of "board creation time" memory leaks.
Fixes: 6f16da53ffe4567 ("hw/arm: versal: Add a virtual Xilinx Versal board")
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190104104749.5314-2-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/tracetool/backend/syslog.py')
0 files changed, 0 insertions, 0 deletions