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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-09-03 19:00:04 +0200 |
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| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-21 13:19:02 +0200 |
| commit | 45e5dc43b3dab096bedf0d537e9b99ee169d0784 (patch) | |
| tree | c30f3fdff1aa67084b627df6fe4cc2c23e07ffa3 /scripts/undefsym.py | |
| parent | 6a9e5cc61c52af53c71ac24411324427650e6755 (diff) | |
| download | focaccia-qemu-45e5dc43b3dab096bedf0d537e9b99ee169d0784.tar.gz focaccia-qemu-45e5dc43b3dab096bedf0d537e9b99ee169d0784.zip | |
hw/sd/sdhci: Resume pending DMA transfers on MMIO accesses
If we have pending DMA requests scheduled, process them first. So far we don't need to implement a bottom half to process them. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Message-Id: <20200903172806.489710-3-f4bug@amsat.org>
Diffstat (limited to 'scripts/undefsym.py')
0 files changed, 0 insertions, 0 deletions