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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-09-03 17:31:04 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-21 13:19:02 +0200 |
| commit | 9321c1f2d08817fdb90ad129fbe3194207e73ba0 (patch) | |
| tree | ea06c8e85fd45b51d6c739ad6345b70f61c101e2 /scripts/undefsym.py | |
| parent | 2bd9ae7e3087a5b853d67ddbedca1b94f88229cf (diff) | |
| download | focaccia-qemu-9321c1f2d08817fdb90ad129fbe3194207e73ba0.tar.gz focaccia-qemu-9321c1f2d08817fdb90ad129fbe3194207e73ba0.zip | |
hw/sd/sdhci: Yield if interrupt delivered during multiple transfer
The Descriptor Table has a bit to allow the DMA to generates Interrupt when the operation of the descriptor line is completed (see "1.13.4. Descriptor Table" of 'SD Host Controller Simplified Specification Version 2.00'). If we have pending interrupt and the descriptor requires it to be generated as soon as it is completed, reschedule pending transfers and yield to the CPU. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Message-Id: <20200903172806.489710-5-f4bug@amsat.org>
Diffstat (limited to 'scripts/undefsym.py')
0 files changed, 0 insertions, 0 deletions