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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-02-15 18:29:37 +0000 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-02-15 18:29:49 +0000 |
| commit | 4f2eff36ad2d8f19a63544ff77b572d307c7f5c9 (patch) | |
| tree | efe16cc43c73c5d58d8a1172d4dc1c63e84c2d10 /scripts/vmstate-static-checker.py | |
| parent | 5a53e2c1dc939fea1af92cc126ee546d8211d412 (diff) | |
| download | focaccia-qemu-4f2eff36ad2d8f19a63544ff77b572d307c7f5c9.tar.gz focaccia-qemu-4f2eff36ad2d8f19a63544ff77b572d307c7f5c9.zip | |
hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling
The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had misimplemented this as making the bits RAZ/WI from both Secure and NonSecure states. Fix this bug by checking attrs.secure so that Secure code can pend and unpend NMIs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-3-peter.maydell@linaro.org
Diffstat (limited to 'scripts/vmstate-static-checker.py')
0 files changed, 0 insertions, 0 deletions