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authorDeepak Gupta <debug@rivosinc.com>2024-10-08 15:49:57 -0700
committerAlistair Francis <alistair.francis@wdc.com>2024-10-30 11:22:08 +1000
commit966f3a38958acf18ae64031c014dcd58e2181211 (patch)
treee5215324a5cecb49f4edb0e862b7ae787801144c /scripts/xml-preprocess.py
parentb039c9611331ccf61a53b2d26d80a8cfb596e0ce (diff)
downloadfocaccia-qemu-966f3a38958acf18ae64031c014dcd58e2181211.tar.gz
focaccia-qemu-966f3a38958acf18ae64031c014dcd58e2181211.zip
target/riscv: zicfilp `lpad` impl and branch tracking
Implements setting lp expected when `jalr` is encountered and implements
`lpad` instruction of zicfilp. `lpad` instruction is taken out of
auipc x0, <imm_20>. This is an existing HINTNOP space. If `lpad` is
target of an indirect branch, cpu checks for 20 bit value in x7 upper
with 20 bit value embedded in `lpad`. If they don't match, cpu raises a
sw check exception with tval = 2.

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241008225010.1861630-8-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/xml-preprocess.py')
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